Copyright (C) 1994,1995,1996,1997 Terumasa KODAKA, Takeshi KONO
■ 2nd CCU (Communication Control Unit)
Target PC-9821Xa16･Xa13･Xa12･Xa10･Xa9･Xa7･Xa7e･Xt16･Xt13･St15･St20･Ra20･
Xb10･Xv13･Xe10･V20･V16･V13･V12･V10･V7･Cx2･Cb2･Cx3･Cb3･Ne3･Nd2･
Na12･Na9･Na7･Nb7･Nx･Lt2
Chip 16550
IR301A
Explanation o As a secondary serial, a chip equivalent to 16550 is installed.
o The presence or absence of the secondary serial interface is determined by
referring to F8E8:0011h bit 3.
o For PC-9821Cx2･Cb2･Cx3･Cb3･Ne3･Nd2･Na12･Na9･Na7･Nb7･Nx･Lt2,
the secondary serial interface is used exclusively for the IrDA communication port,
and the external RS-232C connector is used as the serial port. Not prepared.
o For PC-9821Cx2･Cb2･Cx3･Cb3･Ne3･Nd2･Na12･Na9･Na7･Nb7･Nx･Lt2,
SHARP IR301A is connected to the secondary serial port as an IrDA transceiver IC.
Related I/O 0002h bit 5
F8E8:0011h bit 3
I/O 0238h
Name Send Holding Register (THR)
Receive buffer register (RBR)
Undocumented
function
[READ / WRITE]
bit 7 ~ 0: data
* Read and write data to and from the serial port.
Explanation o Input / output RS-232C data.
o Access is possible only when the DLAB of I/O 023Bh bit 7 is 0.
Related I/O 023Bh bit 7
I/O 0238h
Name Division ratio register (DL)
Undocumented
function
[READ / WRITE]
bit 7 to 0: Division ratio (lower 8 bits)
--------+----------------------
bps | divide ratio register
--------+----------------------
300 | 384
600 | 192
1200 | 96
2400 | 48
4800 | 24
9600 | 12
19200 | 6
38400 | 3
57600 | 2
115200 | 1
--------+----------------------
Explanation o Set the transfer rate of RS-232C. The upper 8 bits of the frequency division
register are set by I/O 0239h.
o Access is possible only when the DLAB of I/O 023Bh bit 7 is 1.
Related I/O 0239h
I/O 023Bh bit 7
I/O 0239h
Name Interrupt Allow Register (IER)
Undocumented
function
[READ / WRITE]
bits 7-4: unused (always set to 0000b)
bit 3: Modem status interrupt (EDSSI)
bit 2: Line status interrupt (ELSI)
bit 1: Send interrupt (ETBEI)
bit 0: Receive interrupt (ERBFI)
1 = permission
0 = prohibited
Explanation o Set the mask state of RS-232C interrupt.
o Access is possible only when the DLAB of I/O 023Bh bit 7 is 0.
Related I/O 0002h
I/O 023Bh bit 7
I/O 0239h
Name Divide ratio register (DH)
Undocumented
function
[READ / WRITE]
bit 7 to 0: Division ratio (upper 8 bits)
Explanation o Set the transfer rate of RS-232C. The lower 8 bits of the frequency division
register are set by I/O 0238h.
o Access is possible only when the DLAB of I/O 023Bh bit 7 is 1.
Related I/O 0238h
I/O 023Bh bit 7
I/O 023Ah
Name Interrupt Reference Register (IIR)
FIFO control register (FCR)
Undocumented
function
[READ]
bit 7,6: FIFOs
00b = 8250,16450 compatible character mode
01b = FIFO enabled, not used
11b = FIFO enabled, used
bit 5,4: unused (always 00b)
bit 3 to 0: Interrupt factor register (IIR3 to 0)
0001b =
0110b = Receive line, status interrupt
* Overrun error, parity error, framing error Occurs when a break is detected
* Canceled when reading LSR
0100b = Received data valid interrupt
* Received data is valid
* Canceled when read from RBR
1100b = Character timeout interrupt
0010b = Send Holding Register Empty Interrupt
* The transmit holding register is empty
* Canceled by reading IIR or writing to THR
0000b = Modem status interrupt
* Changes in CTS, DSR, RI, DCD
* Canceled when MSR is read
[WRITE]
bit 7,6: Receive interrupt trigger level (RCV_TLVL)
00b = 1 byte
01b = 4 bytes
10b = 8 bytes
11b = 14 bytes
bit 5,4: Reserved (always 00b)
bit 3: TXDRY terminal mode
1 = mode 1
0 = mode 0
bit 2: transmit FIFO reset
bit 1: Receive FIFO reset
1 = reset
0 = Do not reset
bit 0: FIFO permission
1 = Allow FIFO operation
0 = Prohibit FIFO operation
Explanation o Read the interrupt factor.
o Control the operation of the FIFO.
I/O 023Bh
Name Line Control Register (LCR)
Undocumented
function
[READ / WRITE]
bit 7: Division ratio register permission (DLAB)
1 = divide ratio setting
0 = normal
bit 6: Break transmission (SB)
bit 5: Parity (SP)
1 = Negative logic parity
0 = Positive logic parity
bit 4: Parity (EPS)
1 = even parity
0 = odd parity
bit 3: Parity (PEN)
1 = with parity
0 = no parity
bit 2: Stop bit length
bit 1,0: Data bit length
-----+------+---------
Bit | Data | Stop
210 | bit | bit
-----+------+---------
000b | 5 | 1
100b | 5 | 1.5
010b | 6 | 1
110b | 6 | 2
001b | 7 | 1
101b | 7 | 2
011b | 8 | 1
111b | 8 | 2
----+-------+---------
Explanation o Set the format of the serial signal.
o Set whether to access the division ratio register.
Related I/O 0238h
I/O 0239h
I/O 023Ch
Name Modem control register
Undocumented
function
[READ / WRITE]
bits 7-5: unused
bit 4: Loopback
bit 3,2: General-purpose output
bit 1: RTS
bit 0: DTR
Explanation o Controls the RS-232C signal line.
o RTS is set to 1 when data can be received.
o DTR is set to 1 to indicate that the terminal is ready for communication.
I/O 023Dh
Name Line status register
Undocumented
function
[READ / WRITE]
bit 7: FIFO data error (E_RFIFO)
bit 6: Transmit FIFO Empty (TEMT)
bit 5: Transmit Holding Register Empty
bit 4: Break detection (BI)
bit 3: Framing error (FE)
bit 2: Parity error (PE)
bit 1: Overrun error (OE)
bit 0: Data ready (DR)
Explanation o Refer to the status of received data.
Refer to the RS-232C signal line.
I/O 023Eh
Name Modem status register
Undocumented
function
[READ]
bit 7: DCD
bit 6: RI
bit 5: DSR
bit 4: CTS
bit 3: DDCD
bit 2: DERI
bit 1: DDSR
bit 0: DCTS
Explanation o Read the status of the modem signal line
I/O 023Fh
Name Scratch register
Undocumented
function
[READ / WRITE]
bit 7 ~ 0: Scratch data
Explanation o A port that the programmer can read and write freely. The written value is read out.